Field of the Invention
The present invention relates to a complementary metal oxide semiconductor (CMOS) output circuit.
Description of Related Art
FIG. 14 is a circuit diagram illustrating a conventional example of a CMOS output circuit. A CMOS output circuit Z of this conventional example includes a P-channel MOS field-effect transistor M1 and an N-channel MOS field-effect transistor M2 connected in series between a power supply terminal (VCC) and a ground terminal (GND), so as to drive an output voltage VOUT at the connection node between them, in accordance with ON/OFF states thereof.
For example, when the transistor M1 turned on while the transistor M2 is turned off, the output voltage VOUT becomes high level (≈VCC). In addition, when the transistor M1 is turned off while the transistor M2 is turned on, the output voltage VOUT becomes low level (≈GND). In addition, when both the transistors M1 and M2 are turned off, the CMOS output circuit Z becomes an output high impedance state.
Note that, as an example of a conventional technique related to the present invention (reverse current prevention technique), there is JP-A-2006-228027.
Now, the transistors M1 and M2 integrated in a semiconductor device are respectively accompanied with body diodes BD1 and BD2 illustrated in the diagram. In addition, in the conventional MOS output circuit Z, the back gate of the transistor M1 is connected to the power supply terminal while the back gate of the transistor M2 is connected to the ground terminal.
Therefore, in an operating condition where the body diode BD1 or BD2 is forward biased (for example, VCC<VOUT, or VOUT<GND), even if the transistors M1 and M2 are both turned off, unintended output current IOUT (of a few mA, for example) may flow through the body diode BD1 or BD2 (see a dot-dashed line and a two-dot-dashed line in the diagram).